The present invention is in the field of integrated circuitry as it applies to computerized semiconductor devices and pertains more particularly to methods and apparatus for achieving a symmetric signal propagation delay from input to output in a current mode logic circuit.
A logic gate is an elementary building block of a digital circuit. There are several different types of logic gates. The most basic of these are AND, OR, XOR, NOT, NAND, NOR, and XNOR. Generally speaking, a logic gate is defined by a specific truth table that describes required input condition to produce a specific output condition. Most logic gates have multiple inputs and one output. Of course, every terminal in a logic gate assumes a binary condition either 0 or 1 at any given moment in time during operation. These binary conditions are defined by voltage levels applied to the circuit. For example, a low voltage produces a binary 0 and high voltage produces a binary 1. In most logic ICs there is a definitive on and off state and, therefore, a charge storage time to contend with before terminals change state.
A relative recent development in digital logic is known as emitter-coupled-logic (ECL), also known as current-mode-logic (CML). CML is based on the use of a multi-input differential amplifier to amplify and combine the digital signals, and emitter followers to adjust the DC voltage levels. As a result, none of the transistors in the gate ever enter saturation, nor do they ever get turned off completely. The transistors remain entirely within their active operating regions at all times. As a result, the transistors have a much smaller charge storage time to contend with, and can change states much more rapidly. Also the difference between the voltages used to represent the binary values is smaller requiring less charge transfer to change states. Thus, the main advantage of this type of logic gate is extremely high speed.
One issue that one must contend with in a CML multi-input logic gate is that there is an unequal propagation state of individual signal inputs to individual signal outputs through a given array of transistors within a circuit. For example, if one input A/{overscore (A)} is changed, the latency to the output of the circuit it will experience will be La. If B/{overscore (B)} is then changed, the latency to output it will experience will be Lb where Laxe2x89xa0Lb. This phenomenon is troublesome in various applications such as in phase detection circuits used in phase-locked-loop (PLL) synthesizing. It is well known that a phase detector must quantify phase error of an input signal against a timed reference signal. Latency non-equivalence in propagation from input gates to output of the circuit causes an error in the quantification of phase error.
What is clearly needed is a symmetrical transistor structure within a circuit that equalizes latency within a circuit in terms of signal propagation from multiple inputs to output of the circuit.
In a preferred embodiment of the present invention, a multilevel logic gate for processing digital data in a semiconductor application is provided. The multilevel logic gate comprises, two or more signal input leads for receiving signal input, two or more signal output leads for outputting signal results and a symmetrical structure of an even number of transistor circuit pairs for combining and amplifying the input signals, the symmetrical structure directly interfacing the input leads. The symmetrical structure causes any input signal to propagate through the structure to output at a same latency as any other input signal to the structure.
In a preferred embodiment, the gate is implemented in current-mode-logic (CML). In one embodiment, the symmetrical structure is an AND structure. In one embodiment, the symmetrical structure is a NAND structure. In one aspect, there are two separate input voltage ranges applied to the gate, the voltage ranges defined as one higher voltage range and one lower voltage range. In this aspect, an even division of the number of signal input leads connected to inputs on the symmetrical structure are operated at the higher voltage range. The remaining number of signal input leads connected to inputs on the symmetrical structure are operated at the lower voltage range.
In another aspect of the present invention, a method for producing an equal signal-propagation latency from any input on multiple input, multilevel logic gate to any output on the gate is provided. The method includes the steps of (a) duplicating the asymmetric structure of the standard logic gate once for each possible combination of inputs, (b) providing each input simultaneously on all input ranges, (c) connecting each input to a asymmetric structure so that all variations of connecting the inputs to the structure are represented, and (d) connecting the output leads of the asymmetric structures together so that the asymmetric structures balance one another and provide a combined structure that is symmetric overall.
In one aspect of the method, the logic gate is a current-mode-logic (CML) gate. Also in one aspect in step (d), the symmetric structure is an AND structure. In another aspect in step (d), the symmetric structure is a NAND structure. In a preferred application in step (b) there are two separate input voltage ranges applied to the gate, the voltage ranges defined as one higher voltage range and one lower voltage range.
In preferred aspects in step (c), an even division of the number of signal input leads connected to inputs on the symmetrical structure are operated at the higher voltage range, and wherein the remaining number of signal input leads connected to inputs on the symmetrical structure are operated at the lower voltage range. In all aspects in step (d), the output of the symmetrical structure is a weighted sum of the outputs of the asymmetrical structures of step (a).
Now, for the first time, a symmetrical transistor structure is provided within a circuit that equalizes latency within the circuit in terms of signal propagation from multiple inputs to output of the circuit.